The RISC-V Challenge - Getting Into The Ecosystem
For the past few years, I have been waiting for RISC-V to move from an interesting idea to a serious challenger in mainstream computing. The architecture has matured steadily, every year brings new microcontrollers based on the ISA, improved toolchains, and broader operating system support. All of this makes one thing crystal clear; RISC-V is no longer a research novelty, but a serious architecture.
By far one of the most important milestones was upstream support in the Linux kernel. Once Linux support stabilised, the conversation shifted from “can it run software?” to “where can we deploy it?” This was crucial for RISC-V as operating system support accelerates everything: compilers improve, drivers appear, distributions take notice, and developers gain confidence. At last, the RISC-V software barrier is steadily eroding (if not slowly becoming irrelevant).
However, RISC-V still faces a very serious structural hurdle, but has nothing to do with instruction encoding. The problem that RISC-V faces is ecosystem infrastructure, particularly in the processor and motherboard space. For example, if you want to build a system around x86 from Intel or AMD, or around ARM cores licensed from Arm Ltd., you can purchase off-the-shelf motherboards, validated chipsets, firmware stacks, and a mature supply chain. RISC-V, sadly, does not yet enjoy that convenience in general-purpose computing. There are development boards, certainly, and some are well engineered, but development boards are not the same as a stable, multi-vendor desktop and server ecosystem with defined sockets, long-term availability, and guaranteed platform compatibility.
Interestingly, microcontrollers have been RISC-V’s natural entry point (such as the WCH32V range)m but such devices are application-specific, tightly integrated, and often deployed in controlled environments. Now, microcontrollers are a logical starting ground, but they do not define the future of general-purpose computing. Web browsing, virtualisation, enterprise workloads, high-performance computing, and cloud infrastructure require scalable processor platforms with standardised interfaces and predictable upgrade paths.
Until RISC-V secures a foothold in that domain, it remains adjacent to mainstream computing rather than embedded within it.
RISC-V Processor Demonstrated on Intel 3 Process Node
Europe has pursued domestic silicon capability for years, often in parallel with similar efforts in Asia and the US. Recently, researchers at Barcelona Supercomputing Center and its Barcelona Zettascale Lab under the European Processor Initiative developed the worlds first RISC-V processor targeted at Intel’s 3 node.
Early in development of the TC1 RISC-V CPU, access to cutting-edge fabrication was limited, so the RTL was validated using TSMC N7 as a proxy node. Once this was proven to work and fully validated, fabrication of the CPU was then shifted to the Intel 3 EUV node from Intel. The resulting die measures 15.2 mm², with a 3.2 mm² CPU subsystem and integrated PCIe Gen5 and DDR5 interfaces.
Architecturally, TC1 integrates three heterogeneous RISC-V cores across independent tiles: Sargantana, Lagarto Ka with vector support, and Lagarto Ox. Considering how modern computing needs are changing, heterogeneous integration is a sensible design choice as it allows optimisation for different workload characteristics without duplicating unnecessary silicon (i.e. having 8 of the same core rarely makes sense these days where AI and other specific data tasks are needed).
Furthermore, a subsequent batch of 500 chips demonstrated high functional yield, and most units were able to get all three cores to function, achieving frequencies up to 1.25 GHz, exceeding pre-tapeout expectations. For a first silicon effort on a new node and architecture combination, that is a brilliant outcome, and shows that RISC-V is capable of operating on advanced process nodes without being treated as an academic exercise.
How Could RISC-V Approach the Processor Problem?
Demonstrating silicon on a leading-edge process is an incredibly important milestone as it proves technical feasibility. However, it does not automatically create a market for such devices.
RISC-V’s openness is both its strength and its risk. Because anyone can design a RISC-V processor, fragmentation is almost inevitable, with different vendors choosing different packaging strategies, power delivery requirements, firmware models, and board-level interfaces. Innovation will certainly flourish, but compatibility may suffer tremendously.
Mainstream RISC-V adoption, as such, will require serious standardisation at the platform level. If the industry as a whole can agree on a defined motherboard form factor, CPU socket, electrical pinout, and firmware baseline, the barrier to entry would collapse. A motherboard vendor could design a single board capable of accepting processors from multiple RISC-V manufacturers, giving RISC-V the interoperability that allowed x86 platforms to dominate desktops and servers for decades.
Such a model would also remove significant restrictions from hardware manufacturers encouraging competition at the silicon level while preserving stability at the platform level. In fact, such common packages used in desktops could extend into entry servers and potentially scale upward, eroding the line between personal and business computing. Hardware longevity would further improve because users could upgrade processors without discarding entire systems that are still perfectly usable.
Whether this level of cooperation will happen is uncertain, especially when considering that commercial incentives often favour proprietary ecosystems. Still, RISC-V’s philosophical foundation is based on openness, and if that openness extends beyond the ISA and into platform design, the architecture could redefine how computing hardware is standardised and deployed.
RISC-V is not guaranteed to reshape the industry, nothing is, but it has already moved further than many expected. The next phase will not be defined by instruction sets or compiler support, but defined by whether the industry can align around shared hardware foundations instead of repeating the fragmentation cycles of the past.
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