iDEAL Semiconductor SuperQ 200V MOSFETs Push RDS(on) Lower in Standard Packages

Power engineers working in the 200 V space tend to run into the same constraint sooner or later. Efficiency improvements start slowing down even while switching frequencies climb and power density continues creeping upward. The silicon itself is usually the limiting factor. Packaging, cooling, and layout tricks help, but once conduction losses dominate the power stage there is only so much margin left to reclaim. Designers end up squeezing a few milliohms here and there while the rest of the system keeps demanding more current.

SuperQ Silicon Targets Conduction Loss Limits in 200 V Designs

iDEAL Semiconductor is addressing that problem with its SuperQ 200 V MOSFET platform, which now includes devices pushing on-resistance further down inside familiar power packages. Instead of introducing new mechanical formats, the company is focusing on improving the silicon inside packages engineers already design around.

One example appears in the iS20M5R5S1T device. The part fits into the widely used TOLL footprint, yet its maximum on-resistance drops to around 5.5 milliohms while still supporting a 200 V drain rating. In practical designs that number matters less as a headline specification and more as a thermal lever. A few milliohms shaved off conduction loss can remove several watts from a high-current stage once currents climb into the hundreds of amps.

That shift shows up clearly in motor drive stages where conduction losses dominate large portions of the operating cycle.

TOLL and TO-220 Options Reflect Different Thermal Realities

Two devices illustrate how the platform is being positioned. The TOLL-packaged iS20M5R5S1T focuses on compact surface-mount layouts where thermal spreading across copper planes and heatsinks becomes critical once current climbs. In that configuration the device can handle currents approaching 150 A while operating up to around 175°C junction temperature.

The companion device takes a different approach. The iS20M6R3S1P appears in the classic TO-220 package, still common in systems that rely on direct heatsinking or mechanical mounting. Here the maximum on-resistance rises slightly to roughly 6.3 milliohms, but the package supports higher current capability approaching 170 A depending on thermal conditions.

Engineers rarely choose between those packages purely on electrical performance. Assembly methods, cooling strategy and mechanical constraints usually dictate which one survives the design review.

Paralleling Behavior and Short-Circuit Survivability Matter More in Motor Drives

Motor drive stages push MOSFETs into operating regions where ruggedness matters as much as raw efficiency. Devices that parallel easily simplify layout and current sharing. In this case the threshold voltage distribution sits within about half a volt across devices, which tends to make current balancing less troublesome once multiple devices are placed in parallel.

Short-circuit behavior also enters the conversation quickly in motor applications. Fault conditions can develop extremely quickly once switching devices lose control of the current path. The SuperQ devices include high short-circuit withstand capability together with avalanche robustness verified through production UIS testing. Those characteristics rarely appear in marketing headlines, yet they tend to become the first question during design validation. You normally discover how valuable that margin is during fault testing.

Additional Package Variants Extend the Same Silicon Platform

The current devices represent only part of the roadmap. Additional versions are planned using the same silicon performance level but packaged for different thermal strategies. One upcoming variant uses a D2PAK-7L footprint suited for high-current surface-mount systems that rely heavily on copper spreading and mechanical reinforcement. Another variant moves toward a TOLT configuration intended for compact layouts where top-side cooling becomes attractive.

Those options hint at a broader strategy. Instead of forcing designers to adopt unfamiliar package formats, the silicon improvements travel through footprints engineers already understand.

Sometimes that small detail makes the difference between evaluating a new device and redesigning an entire power stage around it.

Learn more and read the original announcement at www.idealsemi.com