Chinese University Creates 3D Chip Design Tool for Huawei’s Logic Folding Architecture

Recently we covered Huawei’s development of a LogicFolding technology to increase device density, but now researchers from China have created a tool to help convert chip designs into 3D folded structures. What exactly does the tool do and why could technologies like Logic Folding be the future for semiconductors?  

Chinese University Creates 3D Chip Tool to Support LogicFolding

Peking University's School of Integrated Circuits has recently developed a prototype electronic design automation (EDA) tool designed specifically for Huawei's LogicFolding 3D chip architecture. Unlike conventional semiconductor design flows, which optimise chips as a series of 2D layers before packaging them together, the new tool treats the chip as a single unified 3D structure from the beginning of the design process.

LogicFolding itself differs from conventional 3D packaging technologies. Rather than stacking multiple completed dies together using chiplet packaging, LogicFolding aims to integrate active circuitry throughout the vertical structure of a single chip. This reduces the distance that signals need to travel between logic elements, potentially lowering resistance and capacitance while improving performance and power efficiency.

The research tool aligns with Huawei's recently announced LogicFolding architecture and Tau Scaling Law, presented at IEEE ISCAS 2026. According to Huawei, the approach could eventually achieve transistor densities comparable to 1.4 nm-class manufacturing processes by 2031 without requiring EUV lithography, although these remain long-term research goals rather than commercially demonstrated products.

While the EDA tool has yet to be released publicly, early testing using open-source circuit designs reportedly demonstrated around a 30% reduction in internal wire length, together with improvements in both performance and thermal characteristics compared to conventional design approaches. The creation of an EDA tool is arguably just as important as the semiconductor technology itself. New chip architectures are only practical if engineers have software capable of designing them, and moving from traditional 2D layouts into fully integrated 3D structures introduces an entirely new level of complexity.

The work also demonstrates China's continued effort to develop its own semiconductor design ecosystem. Today, companies including Synopsys, Cadence, and Siemens dominate the global EDA market, with most advanced digital semiconductor development relying heavily on their software. China remains dependent on many of these foreign tools, making domestic alternatives an important strategic objective.

However, it should also be recognised that the Peking University software remains a research prototype. Production-grade EDA tools require years of validation, foundry integration, and industrial testing before they can be relied upon for commercial semiconductor production. Huawei has also indicated that LogicFolding is intended for future Kirin processors, but both the hardware architecture and supporting software will require considerable development before widespread deployment becomes possible.  

Why Could Technologies Like LogicFolding Become the Future of Semiconductors?

Designing modern semiconductor devices is already one of the most complicated engineering challenges in existence. Every transistor must be carefully positioned, while billions of connections have to be routed in such a way that signals arrive on time, power consumption is minimised, and unwanted electrical effects such as resistance and capacitance are kept under control. Modern processors can now contain well over a billion transistors, making manual design impossible. Instead, engineers describe circuits using hardware description languages, while sophisticated EDA software automatically places and routes logic blocks. Even with these tools, however, creating a competitive processor remains an enormously difficult task.

Thus, moving from two-dimensional layouts into true three-dimensional chip design makes this challenge significantly harder. Engineers are no longer optimising devices across a flat surface, but throughout an entire volume of silicon. Every additional vertical connection introduces new design constraints involving routing, thermal management, manufacturing, and signal integrity. This is exactly why tools like the one developed at Peking University will become increasingly important if 3D semiconductor architectures are to become commercially viable.

The timing is also significant because conventional transistor scaling is becoming increasingly difficult. Although manufacturers continue to improve semiconductor processes, each new process node requires substantially greater engineering effort and manufacturing cost than the one before it. Rather than relying solely on making transistors smaller, researchers are increasingly looking at ways of using the third dimension to continue increasing transistor density.

Adding additional active layers dramatically increases the amount of circuitry that can occupy the same footprint. Instead of placing every processor core, accelerator, cache, and I/O interface alongside one another, future chips could distribute these functions vertically, allowing considerably more functionality within the same package size.

The shorter distances between vertically integrated circuits also reduce signal path lengths. Shorter interconnects generally mean lower latency, lower energy consumption, and potentially higher operating speeds, particularly for communication between processing elements that would otherwise be separated by large distances on a conventional 2D die.

Three-dimensional integration could also fundamentally change how memory is incorporated into processors. Instead of placing cache memory beside compute logic, designers could position memory directly above or below processing units, greatly increasing bandwidth while reducing access latency. This is already being explored using technologies such as stacked SRAM and other forms of tightly integrated memory, although it is unlikely to replace technologies such as DRAM entirely, as each serves a different purpose within modern computer architectures.

Overall, three-dimensional semiconductor architectures present engineers with an enormous range of opportunities. If manufacturing costs can be reduced and design tools continue to mature, technologies such as LogicFolding could become one of the most important developments in semiconductor engineering. Rather than relying solely on shrinking transistors, future generations of processors may simply grow upwards, delivering greater transistor density, higher performance, and more capable computing systems than conventional two-dimensional designs can achieve.