As researchers continue to push the limits of what semiconductor technologies can do, it is clear that the next transistor technology to dominate will be the Complementary Field-Effect Transistor (CFET). What challenges do current transistors face, what are CFETs, and how will they empower the future?
What Challenges Do Current Transistors Face?
Since its introduction in 1947, the ability to make transistors smaller has been critical for the semiconductor industry as it allows for improved technology year on year. Smaller transistors not only consume less power, but they can also switch faster, and thus allow for more dense circuits.
However, now that we are starting to approach the atomic scale, making transistors smaller comes with some very real challenges. For example, trying to make features in the nanometers presents challenges with respect to imaging as the wavelength of currently used light far exceeds the size of features on modern transistors. Even using extreme ultra-violet light (EUV), which has a wavelength of just 13.5nm, is still far larger than the size of cutting-edge features, meaning that masks and optical systems are extremely complex, and thus, expensive.
But the problems faced by transistors don’t stop with photo-lithography; once the physical size of a transistor approaches the atomic realm, then all kinds of quantum effects become massive players in transistor behavior. For example, tunneling becomes a very real concern, which results in high leakage currents, poor switching characteristics, and unreliable operation.
Another challenge faced by current transistor technologies is that the use of NMOS and PMOS transistors in CMOS circuits (the most common by far) means that even the simplest logic element requires at least two transistors. This increases the overall space used, thereby limiting the number of logic elements on chips.
Finally, thermal management of current designs is extremely problematic when considering that the number of transistors being packed into modern devices is in the hundreds of billions.
How Complementary Field-Effect Transistors Change This
It is clear that current transistor technologies will struggle to sustain technological development as we progress into the future, but there is a solution; Complementary Field Effect Transistors (CFET).
The reason why CFET is likely to be the next major leap in semiconductor technologies comes down to the fact that it is fundamentally different from current technologies used by Intel and AMD. As the name suggests, a CFET is a combination of N and P type transistors stacked on top of each other, effectively doubling the number of transistors on any given chip, making it perfect for CMOS circuits.
However, this design would not help designs where specific arrangements of transistors are required (such as those found in analogue circuitry). Furthermore, it is important to note that CFETs are still in their infancy, and that their manufacture introduces a whole range of challenges.
Firstly, the use of epitaxial growth layers and high ratios makes it difficult to etch channels and source/drain regions, and this is already causing headache for researchers. Secondly, the use of monolithic integration also introduces challenges with respect to imaging and processing, whereby extremely high aspect ratio structures require specialized imaging systems and chemical processes.
Thirdly, CFETs can be manufactured using a sequential integration process, whereby a base layer of transistors are manufactured, and then additional layers are grown over these transistors. However, this introduces all kinds of challenges with respect to material flexibility, and the need for extremely precise alignment.
Fourthly, the extremely tight tolerance windows needed by CFETs means that any deviation in the manufacturing process can result in failed products, whether through opens, shorts, or misalignment of features.
How Will CFET Technologies Empower the Future?
There is no doubt that CFET will be the next generation of transistor technologies, and will likely become dominant over the next decade. By doubling the number of transistors on any given chip, engineers will rapidly break the 1 trillion transistor barrier, something that the industry has been trying to achieve for years.
At the same time, having such large transistor densities will allow for the creation of extremely powerful processors and SoCs, which will undoubtedly lead to a new era of computing. Devices will have cores containing thousands of CPUs, have access to massive amounts of memory, and run extremely large AI models locally, all while providing users with the ability to create unique software solutions that would normally be too difficult to run on a mobile device.
Furthermore, the use of CFETs will likely see engineers utilizing accelerators more than ever, especially NPUs that have extensive uncommitted logic areas that can be programmed to run any specific accelerator function. As the number of transistors available on a chip increases, so does the complexity of the tasks that it can perform, and the ability to execute accelerators natively on-chip not only improves energy efficiency, but speed of execution as well.
Overall, CFETs clearly present engineers with exciting opportunities, and there is no doubt that when researchers are able to commercialize these technologies, the world will change virtually overnight.
You may also like
