PowerLattice Develops New Power Delivery IC for 50% Less Power Consumption
Recently, a new start-up called PowerLattice has emerged from stealth after raising $25 million in Series A funding led by Playground Global and Celesta Capital. The new company has also reported earlier seed funding of $6 million, bringing its total funding to $31 million.
According to PowerLattice, they say they have developed what they claim is the industry's first power delivery chiplet that can be integrated into AI accelerators, GPUs, and CPUs. The chiplet is said to integrate power delivery directly into the processor package that PowerLattice says allows for a total compute power need reduction of over 50%.
The new technology utilises proprietary technologies including miniaturised on-die magnetic inductors, advanced voltage control circuits, and a vertically stacked design. Furthermore, the use of a programmable software layer allows for dynamic changes to the chiplet's operation depending on the current power and thermal demands of the connected processor.
This move reflects a broader industry shift toward more modular, chiplet-based designs as trying to integrate everything onto a single monolithic part is increasingly seen as impractical and inflexible. By integrating power delivery into the processor package, PowerLattice says it can significantly reduce the length of power delivery paths, lift the power ceiling on processors, and reduce throttling which all result in a processor being able to utilise more of its potential.
As such, PowerLattice says it can double the compute performance of a rack for any given power envelope. At the same time, the new chiplet is positioned to be integrated into chiplet- or package-based designs and modules rather than being grafted into a monolithic system-on-chip; it is more likely to be part of a device package (for example, inside FPGA or CPU packages) than to be directly soldered as a conventional PCB component, which helps to shrink the overall footprint of a processor while providing consistent, precise, and stable power delivery. PowerLattice argues this makes the new chiplet ideal for large-scale AI clusters.
While PowerLattice may claim to be the first to announce this kind of power-delivery chiplet, it will most certainly not be the last; if validated, the approach is likely to appear in high-performance chiplet-based modules and systems.
Why does this matter so much for future semiconductors?
In the field of semiconductors and high-performance computing, power is everything. Not only is power needed to get data moving around, but it’s also needed to manipulate that data.
However, as power consumed by a device increases, so does the amount of heat generated, and this heat must be removed otherwise the device will fail due to hitting its upper thermal limit. This issue is made worse when considering that the need for more power results in a larger device, and thus requires more space for thermal management systems (such as heatsinks).
Additionally, the need for more power also sees an increase in the size of wires and connectors needed to get that power to the device. Again, this leads to a larger footprint and introduces challenges in power distribution, thus requiring even larger heatsinks.
If a device can increase its operating voltage while reducing its current for the same power, resistive losses (which scale with I²R) are reduced, though this depends on the efficiency of the voltage conversion stages. Furthermore, if power delivery systems can be mounted directly onto a chip, or at least located closer to the chip, then the distance travelled by current is significantly reduced, and this helps to minimise losses after regulation (where current consumption can be highest).
The new demonstration from PowerLattice fits into a broader move toward chiplet-based, modular semiconductor designs: rather than forcing every function onto a single monolithic die, designers can partition power delivery and other functions into discrete chiplets. This approach makes prototyping, modification, and on-the-fly adjustments easier, and possibly in the future, chiplet usage could become as simple as pick-and-place processes, enabling rapid swaps when a design changes or a part needs to be updated.
Thus, what PowerLattice has demonstrated could be an important step toward more modular, chiplet-based power delivery for future semiconductors. It is unlikely to be the only approach, and even if it is among the early examples of this kind of device, it almost certainly won't be the last. These kinds of chiplets will likely begin to appear in high-performance chiplet-based modules and systems. While they could potentially be integrated directly into PCBs, they are more likely to be incorporated as part of device packages, for example, alongside FPGAs and CPUs where package-level integration and thermal/power co-design are already common.
How would future devices look with the new PowerLattice chiplet?
There is no doubt that the new chiplet from PowerLattice demonstrates a growing interest in chiplet designs, but what does this mean for future devices?
Trying to integrate everything onto a single piece of silicon is arguably both impractical and inflexible. Designs that are made have to be prototyped, manufactured, and then deployed, and any changes to that design require an entire manufacturing cycle to integrate changes.
Chiplets, however, allow engineers to create designs using smaller chips that can be adjusted on the fly. For example, if chiplet usage can be made as simple as pick and place processes, then a sudden change in the design or chiplet part can be done on the fly with minimal disruption to the manufacturing process.
This is why chiplet-based designs will be highly sought after by engineers, especially in the field of mobile computing where designs need to be able to rapidly change, support new technologies, and deploy updates as needed.
So, will this PowerLattice device be the last of its kind? Absolutely not!
This PowerLattice device may be the first in the world, bu it will most certainly not be the last. It is unlikely in the near term that this device will appear in everyday consumer devices (such as smartphones and laptops), but it will undoubtedly make its way into high-performance chiplet-based modules and systems.
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