RISC-V, the processor ISA that will undeniably change the future of electronics, has had a new addition to its ranks through the release of Micro Magics MagicV 64-bit RISC-V processor. What exactly was announced, and how does this further push RISC-V as the next and only ISA choice for engineers moving forward?
Micro Magic Releases MagicV RISC-V Processor
Recently, Micro Magic announced the release of its MagicV 64-bit RISC-V processor cores, targeting high-performance computing while maintaining extremely low power consumption. The new range comes in 1-, 2- and 4-core configurations, providing engineers and semiconductor developers with different options depending on the amount of computing performance and energy consumption required by their application.
The MagicV architecture supports a wide range of operating systems, including Linux, Zephyr and FreeRTOS, with Micro Magic demonstrating a multicore MagicV implementation successfully running all three platforms.
However, relatively little architectural information has been released, making direct comparisons with other RISC-V cores difficult. Even so, Micro Magic has published several performance and power figures that give an indication of what MagicV is capable of.
According to the company, a single MagicV core operating at 0.8V can reach 4.25GHz and achieve approximately 11,000 CoreMarks while consuming around 200mW. Increasing the voltage to 1.1V allows the same core to reach 5GHz and approximately 13,000 CoreMarks.
Micro Magic also claims that its 64-bit RISC-V architecture can achieve a performance efficiency of approximately 110,000 CoreMarks per watt, placing considerable emphasis on performance-per-watt rather than raw frequency alone.
For particularly power-constrained applications, the company has also developed an ultra-low-power version of MagicV. This implementation reportedly consumes around 10mW when operating at 1GHz while remaining below 500mW at 5GHz.
This ability to alter core count, operating frequency and power consumption means that semiconductor designers can scale MagicV implementations depending on the exact needs of their hardware.
For example, a wearable could prioritise extremely low power consumption with a single core operating at a lower frequency, while a larger embedded or computing platform could instead use multiple cores at considerably higher speeds.
According to Micro Magic, the architecture is being positioned across a surprisingly broad range of applications, including wearables, embedded and connected devices, automotive electronics, smartphones and even rack-mounted servers.
The company is also highlighting small die area, low cost and low-voltage operation as key advantages, offering MagicV as licensable processing technology that semiconductor manufacturers and hardware developers can integrate into their own designs.
This breadth of applications is particularly interesting because it demonstrates how RISC-V is increasingly moving beyond its early association with small embedded processors.
How Does the Micro MagicV Help the RISC-V Community?
While the development of another RISC-V processor core may initially seem like nothing more than another option entering an already growing market, every new RISC-V implementation helps to make the architecture just that little bit more viable for engineers.
And this is arguably one of RISC-V's greatest strengths.
Unlike proprietary instruction sets, RISC-V is an open ISA that can be implemented without traditional instruction-set royalties. This significantly reduces the barriers for companies wanting to develop their own processors and allows vendors to customise implementations while remaining within the wider RISC-V ecosystem.
As more CPU vendors enter the market, engineers gain considerably more choice.
One developer may create a processor specifically optimised for extremely low-power devices, while another could concentrate on high-performance computing. Others could integrate custom acceleration for AI, communications or signal processing.
Yet despite these processors being architecturally different internally, they can still target the same underlying RISC-V software ecosystem where compatible extensions and platform requirements are supported.
This encourages considerably greater competition between processor vendors while allowing software development to be shared across a much larger range of hardware.
Furthermore, because the ISA itself is open, processor designers can study the wider ecosystem, develop extensions and build new architectures without being tied entirely to the roadmap of a single ISA owner.
This could help RISC-V technology advance rapidly as new ideas are introduced by numerous competing companies rather than being dictated by one organisation.
But what makes MagicV particularly interesting is that it is not simply targeting microcontrollers and low-performance embedded systems.
Micro Magic is combining low-power operation with clock frequencies reaching several gigahertz and multicore configurations, while supporting operating systems ranging from FreeRTOS and Zephyr through to Linux.
The same underlying ISA can now appear inside tiny embedded devices, connected products and wearables while simultaneously being developed for smartphones, automotive systems and rack-mounted servers.
Of course, MagicV itself still needs to prove its capabilities in commercial silicon, and Micro Magic's published performance figures will need to be considered alongside real implementations, workloads and competing designs.
But the important point is the direction of travel. Every new RISC-V core gives engineers another choice, every supported operating system makes adoption easier, and every company entering the ecosystem increases competition.
As such, MagicV is a highly welcomed addition to the RISC-V family and another indication that engineers are gaining increasingly viable alternatives to established proprietary architectures such as Arm and x86.
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